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Silicon Labs /EFR32FG23A010F512GM48 /GPIO_S /CDBUSALLOC

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Interpret as CDBUSALLOC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRISTATE)CDEVEN00 (TRISTATE)CDEVEN10 (TRISTATE)CDODD00 (TRISTATE)CDODD1

CDODD1=TRISTATE, CDEVEN1=TRISTATE, CDODD0=TRISTATE, CDEVEN0=TRISTATE

Description

CD Bus allocation

Fields

CDEVEN0

CD Bus Even 0

0 (TRISTATE): The bus is not allocated

1 (ADC0): The bus is allocated to ADC0

2 (ACMP0): The bus is allocated to ACMP0

3 (ACMP1): The bus is allocated to ACMP1

4 (VDAC0CH0): The bus is allocated to VDAC0 CH0
CDEVEN1

CD Bus Even 1

0 (TRISTATE): The bus is not allocated

1 (ADC0): The bus is allocated to ADC0

2 (ACMP0): The bus is allocated to ACMP0

3 (ACMP1): The bus is allocated to ACMP1

4 (VDAC0CH1): The bus is allocated to VDAC0 CH1
CDODD0

CD Bus Odd 0

0 (TRISTATE): The bus is not allocated

1 (ADC0): The bus is allocated to ADC0

2 (ACMP0): The bus is allocated to ACMP0

3 (ACMP1): The bus is allocated to ACMP1

4 (VDAC0CH0): The bus is allocated to VDAC0 CH0
CDODD1

CD Bus Odd 1

0 (TRISTATE): The bus is not allocated

1 (ADC0): The bus is allocated to ADC0

2 (ACMP0): The bus is allocated to ACMP0

3 (ACMP1): The bus is allocated to ACMP1

4 (VDAC0CH1): The bus is allocated to VDAC0 CH1

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data